UART on Xilinx FPGA - Verilog Design, Vitis Software, Hardware
- CategoryOther
- TypeTutorials
- LanguageEnglish
- Total size801.5 MB
- Uploaded Byfreecoursewb
- Downloads43
- Last checkedApr. 06th '26
- Date uploadedApr. 05th '26
- Seeders 7
- Leechers8
UART on Xilinx FPGA: Verilog Design, Vitis Software, Hardware
https://WebToolTip.com
Published 3/2026
Created by Easy FPGA
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Level: Beginner | Genre: eLearning | Language: English | Duration: 15 Lectures ( 1h 20m ) | Size: 498 MB
UART on FPGA: Verilog RTL to MicroBlaze AXI UART Lite
What you'll learn
✓ Explain UART frame structure, baud timing, and parity concepts clearly.
✓ Implement custom UART TX/RX modules in Verilog/SystemVerilog.
✓ Build and verify loopback communication in simulation.
✓ Integrate a MicroBlaze system with AXI UART Lite in Vivado Block Design.
✓ Create and run UART software in Vitis using XUartLite APIs.
✓ Perform hardware/software co-simulation with .elf and RTL together.
✓ Run and debug the design on real FPGA hardware using Vitis debugger.
✓ Choose between RTL and processor-based approaches based on project constraints.
Requirements
● Basic digital logic (flip-flops, FSM, synchronous design)
● Basic Verilog reading ability
● A Windows PC capable of running Vivado/Vitis
● Xilinx FPGA board for full hardware practice (recommended)
Files:
Code:
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