Udemy - VLSI Physical Design - PnR with Cadence

  • CategoryOther
  • TypeTutorials
  • LanguageEnglish
  • Total size1.9 GB
  • Uploaded Byfreecoursewb
  • Downloads14
  • Last checkedApr. 10th '26
  • Date uploadedApr. 10th '26
  • Seeders 1
  • Leechers10

Infohash : 067DAA6C66D6BC562F926BCAC077773911A6AE82

VLSI Physical Design: PnR with Cadence

https://WebToolTip.com

Published 3/2026
Created by Electronics Zone
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Level: All Levels | Genre: eLearning | Language: English | Duration: 10 Lectures ( 3h 58m ) | Size: 2 GB

From Netlist to GDSII: Learn Floorplanning, Placement, CTS, Routing, and Timing Closure using Industry-Standard EDA Tool

What you'll learn
✓ Complete PnR Flow: Understand the step-by-step process of Physical Design from Netlist to GDSII.
✓ Tool Proficiency: Gain hands-on experience with industry-standard Cadence PnR tools.
✓ Floorplanning: Master techniques for die area estimation, I/O placement, and macro placement to optimize chip layout.
✓ Power Planning: Design robust power grids (power stripes/rings) to mitigate IR drop and electromigration.
✓ Placement Optimization: Perform standard cell placement and resolve placement-related congestion and timing issues.
✓ Timing Analysis: Analyze static timing reports and apply optimization techniques to fix setup and hold violations.
✓ Clock Tree Synthesis (CTS): Build balanced clock trees with low latency and skew.
✓ Routing: Execute global and detailed routing to connect all nets without design rule check (DRC) violations.
✓ Chip Finishing: Execute final steps including metal fill insertion and generating the final GDSII stream file for tape-out.

Requirements
● Basic VLSI Knowledge: Familiarity with the CMOS technology and the standard ASIC design flow (Frontend vs. Backend).
● Digital Electronics: Understanding of basic logic gates, flip-flops, and combinational logic.
● Linux Basics: Comfort with the Linux command line (navigating directories, editing files using vi/vim) as most EDA tools run on Linux.Linux Basics: Comfort with the Linux command line (navigating directories, editing files using vi/vim) as most EDA tools run on Linux.
● Timing Concepts (Recommended): A basic understanding of Static Timing Analysis (STA) concepts like setup time, hold time, and clock skew is helpful but not mandatory, as these will be reviewed.

Files:

[ WebToolTip.com ] Udemy - VLSI Physical Design - PnR with Cadence
  • Get Bonus Downloads Here.url (0.2 KB)
    • ~Get Your Files Here !
    • 1. Place & Route Flow.mp4 (71.4 MB)
    • 10. Final Practical PnR Lab using Cadence and exporting GDS.mp4 (685.4 MB)
    • 2. Input Files.mp4 (168.2 MB)
    • 3. Design Import.mp4 (187.4 MB)
    • 4. I O Placement & Specify Floorplan.mp4 (134.3 MB)
    • 5. Power Planning.mp4 (125.3 MB)
    • 6. Placement.mp4 (167.5 MB)
    • 7. Timing Analysis & Timing Optimization.mp4 (117.8 MB)
    • 8. Clock Tree Synthesis & Routing.mp4 (170.1 MB)
    • 9. Chip Finishing.mp4 (166.6 MB)
    • Bonus Resources.txt (0.1 KB)

Code:

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